In a semiconductor device, the electrical connection between a transistor formed on a wafer and metal wiring and between metal wirings is established first by making contact holes on an inter-layer dielectric, that is formed on the upper part of the transistor structure and between wirings, by a dry etching method with the use of plasma, and then by filling a semiconductor or a metal in the contact holes. Particularly for the production of a high-density and high-speed logic device beyond the 90 nm-node, the damascene process, in which trenches and vias are formed by etching an inter-layer-dielectric made of a low dielectric-constant, or low-k, material by a dry etching method, followed by filling the trenches and vias with Cu as a wiring material, and ArF lithography with a 193 nm light source for a finer pattern formation are being used. The dry etching method is a technology by which a mask material represented by a resist is etched and a layer to be processed is etched selectively for providing a wiring layer and base substrate underlying the vias and the contact holes. This method comprises generating plasma from an etching gas introduced into a vacuum chamber with high frequency power applied externally and allowing reactive radicals and ions generated in the plasma to react with the layers on the wafer with high precision.
In general, when a wiring pattern is formed for a semiconductor circuit, an organic bottom-anti-reflection coating (BARC) is formed on the film to be processed, and a resist film is further formed thereon. The BARC is used to prevent an abnormal pattern, caused by interference of laser light serving as a light source for lithography, from being formed. After forming a resist pattern, the BARC is etched, and then the film to be processed is etched (main etching). Since the BARC is made of a material rich in C, similar to the resist, etching of the BARC is carried out by forming a plasma from an introduced mixed gas consisting of a fluorocarbon gas rich in F, such as CF4 or CHF3, a rare gas represented by Ar, and oxygen gas in a pressure range of from 0.5 Pa to 10 Pa, and by controlling the ion energy incident on the wafer in a range of 0.1 kV to 1.0 kV.
The formation of vias and contact holes is carried out by forming plasma from an introduced mixed gas consisting of a fluorocarbon gas such as CF4, CHF3, C2F6, C3F6O, C4F8, C5F8, and C4F6, a rare gas represented by Ar, oxygen gas, CO gas and the like serving as a plasma gas in a pressure range of from 0.5 Pa to 10 Pa, and accelerating ion energy incident on the wafer up to 0.5 kV to 2.5 kV.
In the etching process described above, the resist materials for ArF or later lithography present problems in that the resist etching rate is larger and the surface roughness due to resist damage is more serious compared to those for conventional KrF resist and i-line resist.
Since the etching resistance of KrF resist was sufficiently high compared to that of ArF resist and the device density was not so high for the former, there was no major concern for striation and line-edge-roughness. However, the deterioration of the line-edge roughness due to resist roughness after etching exerts a great influence on the device characteristics. This is particularly so in etching requiring final dimensional accuracy, such as hard mask etching represented by SiO2 for gate electrode formation and SiN mask etching used as a mask for a shallow-trench-isolation process. Further, etching of a low-k material (SiOC film) that is an inter-layer-dielectric, the introduction of which is being pursued for the production of a high-density logic device, is carried out by high-energy ion irradiation using a relatively high bias and in an atmosphere of gas rich in O2. Therefore, striations occur on the pattern sidewalls, and, in addition, pitting of the resist occurs, which is a phenomenon involving the local appearance of holes on unpatterned portions.